This invention relates to an analog/digital converter and, more particularly, to an analog-digital converter ideal for applications where an AGC (Automatic Gain Control) circuit is realized by digital signal processing.
FIG. 1 illustrates an example in which an AGC circuit is constructed in a conventional digital signal processing unit in order to convert analog data into corresponding digital data.
The digital signal processing unit shown in FIG. 1 includes a variable-gain amplifier 101 for amplifying input analog data (an analog voltage) at a predetermined gain in accordance with control executed by a digital signal processor (hereinafter referred to as a "DSP") or microprocessor (hereinafter referred to as an "MPU") 103, an ordinary well-known analog/digital (hereinafter referred to as "A/D") converter 102, and the DSP or MPU 103.
The operation of an AGC circuit which includes the analog/digital converter in the conventional apparatus of this kind will be described.
First, the DSP or MPU 103 initializes (e.g., sets to "1") the gain of the variable-gain amplifier 101 and calculates the average value of the square of the output data from the A/D converter 102. If this value is less than the set value, control for raising the gain of the variable-gain amplifier 101 is performed and the average value of the square of the output data from the A/D converter 102 is calculated again. By repeating this operation, the average value of the square of the output data from the A/D converter 102 eventually becomes larger than the predetermined set value. When this occurs, the gain of the variable-gain amplifier 102 is fixed and AGC processing is performed in accordance with the processing executed by the DSP shown in FIG. 2.
In the operation of the circuit shown in FIG. 2, the average value of the square of the output signal is obtained by a squaring unit 205 and an averaging unit 206. The average value of the square and the set value are added by an adder 204. The constant of a multiplier 201 is controlled using a register 202 and an adder 203 in such a manner that the difference, namely the error, between the average value of the square and the set value becomes "0". Thus, the average value of the outputs attains a constant level.
If, in the digital signal processing unit described above, the number of bits corresponding to the dynamic range of the analog input voltage is greater than the number of bits corresponding to the operational precision of the DSP 103 that is necessary for signal processing, first the analog voltage is amplified to a level capable of being computed by the DSP 103 under coarse control performed by the variable-gain amplifier 101, and then AGC processing is performed under fine control based upon the processing of the DSP 103.
In general, the variable-gain amplifier 101 is capable of being set to any of a number of gains (e.g., 1.times., 2.times., 4.times., 8.times., . . . , etc. ).
A disadvantage encountered in the prior art described above is that an analog circuit such as the variable-gain amplifier 101 is required. This is disadvantageous because the circuit has a complicated construction and its performance is influenced by the characteristics of the various elements that construct it.
Accordingly, in order to widen the dynamic range of the input voltage level, an arrangement should be adopted in which the variable-gain amplifier is eliminated, the precision of the A/D 102 is raised to increase the number of output bits and all AGC processing is performed in accordance with the processing executed by the DSP 103. The foregoing problems can be solved by adopting such an arrangement. Since an A/D converter having a large number of output bits has recently become available at low cost, adopting the above-described arrangement is considered to be effective.
However, if there is an increase in the number of output bits of the A/D converter 102, the number of operational bits of the DSP 103 also must be increased. In addition, even if the AGC processing shown in FIG. 2 is performed upon increasing the number of operational bits, the time needed for the gain to converge is prolonged greatly in a case where the dynamic range of the input data has been widened. This represents another problem.
In order to solve this latter problem, AGC of the kind shown in FIG. 3 can be adopted. However, when AGC processing of this type is realized by a DSP, an enormous amount of processing is required to be performed by a divider 301 and a square-root unit 302. As a consequence, the time required for processing is great and this arrangement does not offer a truly practical solution.